EDN

The design of LVDS interface for a Multi-Channel A/D Converter

This article analyzes system design specifications for a low-voltage differential serial output interface of a multi-channel, high-speed analog-to-digital (A/D) converter. Maximum data speed is ...
Semiconductor Engineering

The Design Challenges Of Clock Integrity And Clock Jitter

Races, missed next-state values due to long paths, and metastability can result from corrupted clock signals. This post describes the challenges of clock network and clock jitter analysis in more ...
Electronic Design

Clock Generator Keeps The Pace For XDR Interface

To support the recently released Yellowstone high-speed memory interface, now renamed the extreme data rate (XDR) interface, designers at Rambus Inc. and Integrated Circuit Systems Inc. jointly... To ...
Design-Reuse

Design Transition from Sync to Async: Design and Verification Challenges

Synchronous interfaces involve a single clock domain and are relatively easy to design. However, at times, it is advantageous and necessary to have an asynchronous interface between peripherals for ...
Electronic Design

Design A Clock-Distribution Strategy With Confidence

Clock-distribution devices create multiple copies of a master clock and distribute them to a variety of integrated circuits. They accept single-ended or differential clock inputs and supply multiple ...
EDN

Design faults leading to clock and data glitches

With the increasing complexity of SoCs, multiple and independent clocks are essential in the design. The design specifications require system level muxing of some of these clocks before they are sent ...