mccormick.northwestern.edu

COMP_ENG 303: Advanced Digital Design

Overview of digital logic design. Implementation technologies, timing in combinational and sequential circuits, EDA tools, basic arithmetic units, introduction to simulation and synthesis using ...
Embedded

Configuring a PSoC for a DIY oscilliscope/logic analyzer – Part 2

Select between the Combination or Sequential circuit for analysis (Figure 16). Figure 16: Screen to select Combinational or Sequential Circuit Select the number of inputs (max of 3) and number of ...
Design-Reuse

Latches and timing closure: a mixed bag

Digital blocks contain combinational and sequential circuits. Sequential circuits are the storage cells with outputs that reflect the past sequence of their input values, while output of the ...
EDN

A novel approach for simulation of digital circuits using levelization

Verification had always been an important part of SOC design flow. As SOCs are getting more and more complex, so is their verification. Verification of a design involves simulating the all possible ...
Design-Reuse

Averant's Solidify 6.5 Significantly Improves Combinational and Sequential Equivalency Checking and Clock Domain Crossing Checks

Oakland, Calif. – December 12, 2017 – Averant Inc., the First In Formal™ leader in property verification of RTL designs for digital circuits, today announced the release of Solidify 6.5. Some of the ...
Electronic Design

Reduce Power in Chip Designs with Sequential Clock Gating

Clock gating is one of the most frequently used techniques in RTL to reduce dynamic power consumption without affecting the functionality of the design. One method involves inserting gating conditions ...