Business Wire

Aldec Brings Assertions to FPGA Designers with the Release of Active-HDL 8.1

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-language simulation for ASIC and FPGA devices, announced today the release of Active-HDL 8.1. The new release introduces a ...
Business Wire

Aldec’s Active-HDL Verification Capabilities Enhanced to Support SystemVerilog Constructs and UVM

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has greatly enhanced the verification ...
EDN

Aldec simulator links to Simulink

SAN JOSE, Calif. — ASIC and FPGA verification tool vendor Aldec Inc. has added a cosimulation wizard to its Active-HDL simulation environment to connect the environment to Mathworks' Simulink. The new ...
Semiconductor Engineering

HDL Simulation Acceleration Solution For Microchip FPGA Designs

A way to accelerate a HDL simulation for a system FPGA design that includes the custom logic and reused IP cores where the testbench executes in the simulator and the synthesizable parts of the design ...
Electronic Design

Facing Up To Today’s FPGA Verification Challenges

Today it is not unusual for FPGA users to have to deal with more than one language in their designs. At earlier stages of the design development it may be necessary to interface HDL simulation with ...
EDN

HDL tool upgrades lint, simulation

The HDL Companion version 2.0 design analysis, navigation, and, editing environment adds VHDL/Verilog linting, plus improved readability and simulation/synthesis performance. The tool automatically ...
Semiconductor Engineering

Re-using Common Simulation Set-Up Processes To Speed Regression

Functional verification of SoCs always has some kind of set up process. For complex SoCs, at least, this initial set up phase often consumes from 20 to 90% of each test’s total simulation time. And ...