Design-Reuse

Mapping LMS Adaptive Filter IP Core to Multiplier-Array FPGA Architecture for High Channel-Density VOIP Line Echo Cancellation

The LMS adaptive filter is the main functional block in high channel-density line echo cancellers for VOIP. In this paper, we describe an LMS adaptive FIR filter IP and estimate its performance when ...
EDN

Architecture-oriented C optimization, part 1: DSP features

Part 2 looks at memory-related optimizations. It will be published September 3. Know your hardware! That's what it's all about. Using programming guidelines derived from the processor's architecture ...
Design-Reuse

Design and implementation of Parallel and Pipelinined Distributive Arithmetic based Discrete Wavelet Transform IP core

The Discrete Wavelet Transform (DWT) has gained the reputation of being a very effective signal analysis tool for many practical applications. This paper presents an approach towards VLSI ...
EDN

FIR Filters and FFTs with 28-nm Variable-Precision DSP Architecture

Across a range of applications, the two most common functions implemented in FPGA-based high-performance signal processing are finite impulse response (FIR) filters and fast Fourier transforms (FFTs).