EDN

Tabula Releases 100G Ethernet Packet Parser Reference Design Kit

The new 100 GbE packet parser represents a novel approach to this class of network functions, delivering a unique combination of programmability and low latency currently not achievable on a ...
EDN

Verific Design Automation’s Netlist Only Parser, Database

Verific Design Automation, best known for its Verilog, SystemVerilog and VHDL parsers and elaborators, today said that its Netlist Only Parser is gaining momentum among electronic design automation ...
Electronic Design

First Commercial Parser Ships For System Verilog

A sure sign that a design language is making its way into the mainstream is the appearance of a spate of tools supporting it. For SystemVerilog devotees, the latest good news is the commercial ...
InfoQ

Implementing High Performance Parsers in Java

Unlock the full InfoQ experience by logging in! Stay updated with your favorite authors and topics, engage with content, and download exclusive resources. Vivek Yadav, an engineering manager from ...
Design-Reuse

Tabula Releases 100G Ethernet Packet Parser Reference Design Kit

SANTA CLARA, Calif. -- June 5, 2013 – Tabula Inc., advancing high-performance programmable logic solutions for network infrastructure systems, today announced the availability of the latest addition ...
InfoQ

Implementing High Performance Parsers in Java

Unlock the full InfoQ experience by logging in! Stay updated with your favorite authors and topics, engage with content, and download exclusive resources. Vivek Yadav, an engineering manager from ...