Detailed and precise hierarchical design planning is essential to achieving closure on large designs. In this article we describe a new hierarchical design flow and its usage on a 3 million-gate chip.

Editor's Note: In Part 3 of this series, consultant and ASIC designer Tom Moxon covered several RTL and logic synthesis design flows. In this installment of the series, he'll describe new physical ...

But maybe part of the problem isn’t the meetings themselves, but the physical environment and the social norms we’ve constructed around them. For instance, most conference rooms today are anchored by ...

The FICS Research Institute (University of Florida) has published a new research paper titled “Secure Physical Design.” This is the first and most comprehensive research work done in this area that ...

In today’s highly competitive semiconductor industry, chip-design companies strive for competitive advantages by optimizing designs for PPA (Power, Performance, Area). Along with the functional logic, ...