Semiconductor Engineering

Next-Generation Distributed Static Timing Analysis On The Cloud

Ever-growing chip size and complexity put pressure on every step and every electronic design automation (EDA) tool in the development flow. More decisions must be made at the architectural stage, ...
EDN

Synopsys Rolls Out Transistor-Level Static Timing Analysis

To address emerging custom circuit design challenges, Mountain View, Calif.-based EDA giant Synopsys Inc. today unveiled its anticipated next-generation transistor-level static timing analysis tool, ...
Nasdaq

Synopsys, TSMC and Microsoft Azure Deliver Highly Scalable Timing Signoff Flow in the Cloud

Significant throughput gains with PrimeTime timing signoff and StarRC extraction for multi-scenario, distributed processing runs Considerable cost savings by optimal utilization of cloud computing ...
Embedded

Static timing analysis: bridging the gap between simulation and silicon

Static Timing Analysis (STA) not only acts as a connecting link between backend and frontend design activities, but more importantly helps in bridging the gap between simulation and silicon. STA is ...
Semiconductor Engineering

The Demise Of Static Timing Verification?

The chip industry traditionally has relied on margins to help them mitigate timing problems, but an increasing array of factors are now influencing timing. Can static timing analysis evolve to address ...
Electronic Design

Interview: Cadence's Anirudh Devgan Talks About Parallel Timing Closure Signoff

System-on-Chip (SoC) developers are creating larger and more complex solutions. Static timing analysis and closure is key to successful solution so timing sign off tools can have a significant impact ...
EDN

Rail analysis for SoC ASICs

Rail analysis for an ASIC system on chip (SoC) falls into two broad categories, static and dynamic (also known as transient). Static analysis is driven by power consumption for the average situation, ...