Design-Reuse

AMIQ EDA Releases the DVT Debugger Add-On Module for the e language, SystemVerilog, Verilog, and VHDL

AMIQ EDA, a pioneer in integrated development environments (IDEs) for hardware design and verification and a provider of platform-independent software tools for efficient code development, today ...
EDN

Next-generation Verilog rises to higher abstraction levels

SAN JOSE, Calif. — A radically revised Verilog language took shape at the International HDL Conference here, as presenters unveiled a language reaching toward much higher levels of abstraction.
Design-Reuse

Cadence OVM SystemVerilog Solution Enables More Thorough Verification and Reduces Costs at Mitsubishi Electric

SAN JOSE, Calif., 25 Jan 2010-- Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced today that Mitsubishi Electric Corp. has adopted Cadence® ...
EDN

A real solution for mixed signal SoC verification

As more complex, mixed signal System on Chip (SoC) designs continue to stress verification methodologies and schedules, designers need new approaches in solving today's test challenges. Mixed signal ...