EDN

Take scan test out of the critical path

Integrated circuit complexity and integration continuously advances, posing challenges to the development process. Market profitability, however, demands that products be designed and produced as fast ...
EDN

Smart test for nanometer designs

When semiconductor devices had geometries of 0.18 microns and larger, most defects manifested themselves as static faults. Test strategies based on stuck-at fault-model scan patterns and standard ...
Electronic Design

Reduce Test/Diagnosis Cost with Optimized Scan-Pattern Ordering

Download this article in PDF format. Finding the right balance among test cost, test quality, and data collection for running diagnosis requires consideration of several competing factors. Luckily ...
Electronic Design

Using Timing Constraints For Generating At-Speed Test Patterns

Handling timing exception paths in ATPG tools while creating at-speed patterns has always been a tough and tricky task. It is well understood that at-speed testing is a requirement for modern ...