Experts At The Table: The pressure on verification engineers to ensure a device will function correctly has increased exponentially as chips become more complex and heterogeneous. Semiconductor ...

Philippe Luc, director of verification at Codasip, talked to students of the UK Electronics Skills Foundation (UKESF) about what it is like to be a verification engineer. On one hand the UKESF ...

The complexity of DRC rules increases with shrinking geometries. It is not that the laws of physics change with shrinking IC feature size; they are just more strictly enforced. At one time, there was ...

With the cost of design skyrocketing, EDA must hasten its transition from a hardware-centric industry to a software-centric one. Meanwhile, look for virtual platforms and transaction-level modeling to ...

Each generation of IC design technology introduces new levels of complexity, and logic verification teams face a host of new challenges due to this dramatic rise in IC design complexity. As a result, ...

1. In a big company, doing ASIC design verification for a WCDMA modem for 3G cellular chips. 2. Small company, doing Embedded Software Programming. Working on the design and implementation of layer 1 ...

How formal verification is able to find bugs before signoff. Formal verification’s ability to mathematically prove exhaustively that a chip design meets a set of assertions. Formal techniques are ...