Business Wire

Mentor Graphics Questa Vanguard Program Drives Expansion of SystemVerilog Ecosystem; Third-Party Verification IP Qualified with Questa

Membership in the Questa Vanguard Program is open to those companies who work with Mentor Graphics verification customers and wish to promote the development and use of EDA tools, verification IP, ...
Design-Reuse

Breaking the Language Barriers: Using Coverage Driven Verification to Improve the Quality of IP

Technology advances allows for the creation of larger and more complex designs. This poses new challenges, including efforts to balance verification completeness with minimization of overall ...
Design-Reuse

Cadence OVM SystemVerilog Solution Enables More Thorough Verification and Reduces Costs at Mitsubishi Electric

SAN JOSE, Calif., 25 Jan 2010-- Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced today that Mitsubishi Electric Corp. has adopted Cadence® ...
EDN

How to raise the RTL abstraction level and design conciseness with SystemVerilog – Part 2

As discussed in Part 1, this article proposes four steps to raise the abstraction level of current Verilog HDL designs and provide a phase wise approach to migrate to SystemVerilog. In Part 1 we ...