InfoQ

GraalVM Native Image on RISC-V

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Semiconductor Engineering

Linting RISC-V Designs

As the open-source RISC-V instruction set architecture (ISA) continues to gain momentum, the growing number of RISC-V design solutions and their flexibility creates a problem when choosing the most ...
Electronic Design

Techniques to Minimize Code Footprint in RISC-V-Based Apps

RISC-V supported standard extensions. Hints to help the compiler make better decisions. Reasons why to avoid writing "clever code." 1. These are the standard ...
Semiconductor Engineering

RISC-V Is Thriving: Here’s What You Need to Know

RISC-V, the open-standard Instruction Set Architecture (ISA) conceived by UC Berkeley developers in 2010, is going from strength to strength. The RISC in RISC-V stands for Reduced Instruction Set ...
Electronic Design

Working with High-Level-Language Debuggers in RISC-V-Based Apps

What are the RISC-V External Debug Support Version 0.13.2 specifications? Advantages of a using high-level-language debugger. The role of the ubiquitous breakpoints in debugging. How trace is ...
Design-Reuse

RISC-V: The Open-Source Revolution in CPU Architecture

RISC-V is an open-source Instruction Set Architecture (ISA) that rapidly transforms the CPU design and development landscape. Unlike proprietary ISAs, RISC-V allows free access to architecture ...
CNX Software

FOSDEM 2026 schedule – Embedded, RISC-V, Robotics, Rust, Open Hardware, and more

FOSDEM 2026 will take place on January 31-February 1, with thousands of developers meeting in Brussels to discuss open-source ...
ZDNet

RISC-V, the Linux of the chip world, is starting to produce technological breakthroughs

A decade ago, an idea was born in a laboratory at the University of California at Berkeley to create a lingua franca for computer chips, a set of instructions that would be used by all chipmakers and ...